1. Field of the Invention
The present invention relates to the storage of information by altering the operational characteristics of a transistor within an array of memory transistors and, more particularly, to a non-volatile memory such as a read only memory (ROM).
2. Description of the Related Art
Difficulties are encountered when attempting to increase the storage density of mask ROMs following conventional strategies. Alignment of the code mask during programming is important to the proper storage of information within mask ROMs. The need to achieve precise alignment in a production environment makes it difficult to further reduce the size of the field effect transistors used in forming the mask ROM while still obtaining acceptable throughput and yields. Certain of these difficulties in reducing the size of mask ROMs are discussed below.
A portion of a mask ROM 10 is schematically illustrated in FIG. 1 as including a parallel array of word lines WL and a parallel array of bit lines BL. In the illustrated ROM, bit lines BL are typically heavily doped regions buried in the substrate. The bit lines function as source/drain regions for the memory FETs, with the channel regions of the memory FETs extending between adjacent ones of the bit lines. Word lines extend over and perpendicular to the bit lines, acting as FET gate electrodes to define the locations of the channel regions of the various memory FETs. The memory FETs thus consist of a portion of a pair of adjacent bit lines and the portion of the word line extending between the adjacent bit lines. In such a "shared bit line" configuration, the bit lines are alternately charged to a high potential (e.g., V.sub.CC) or to a low potential (e.g., ground). Programming of the ROM 10 is performed by selecting the performance characteristics of the FETs located at the intersections between the word lines WL and pairs of bit lines BL. For example, data may be stored in the ROM by selecting the threshold voltages for each of the field effect transistors within the array of memory FETs. A logical zero may be stored in field effect transistor 12 by causing FET 12 to have a relatively low threshold voltage; a logical one may be stored at field effect transistor 14 by causing FET 14 to have a relatively high threshold voltage.
Data read operations consist of applying a first (e.g., high) potential to a first bit line, a second potential (e.g., low) to a second bit line, and a read potential to the word line associated with the memory transistor being addressed. For typical NMOS FETs, a read potential applied to the gate of a FET having a low threshold voltage will turn the FET on, allowing current to flow through the FET in a manner which tends to equalize the potentials on the adjacent bit lines. If, on the other hand, the threshold voltage of the addressed FET is high, the read potential applied to the gate will not turn the FET on, current will not flow through the FET, and the respective voltages on the bit lines will not change. The "ON" or "OFF" state of the FET can be then sensed using a differential amplifier connected across the bit lines. FETs having a low threshold voltage, so that a read voltage turns the FET "ON", can be chosen to represent a logical zero and the other, high threshold voltage can be considered to represent a logical one. Thus, logical data can be stored in the ROM array by selecting the threshold voltages of individual FETs in the array of memory FETs.
FIG. 2 illustrates a conventional configuration of a portion of the FIG. I ROM. The bit lines are shown as a parallel array of "buried" lines 22, 24, 26 and 28 formed as N.sup.+ implantations into a P-type silicon substrate 20. Lines 22 and 26 are shown connected to a potential source V and lines 24 and 28 are connected to a lower potential source, such as ground, so that lines 22 and 26 are FET drains and lines 24 and 28 are the sources of the memory FETs in the illustrated ROM. As discussed above, it is possible that the actual voltages present on the bit lines will be different from those illustrated and the voltages will typically be present on the lines only during read operations. A second array of conductive lines WL0, WL1, etc., is formed from, for example, a layer of doped polysilicon deposited on an insulation layer formed over the buried N.sup.+ lines 22, 24, 26 and 28. Word lines WL0, WL1, etc., are formed perpendicular to the implanted buried N.sup.+ bit lines and form the gates of the FETs of the ROM. To form relatively low threshold voltage transistors at selected ones 30 of the transistor positions and to form relatively high threshold voltage transistors at the other transistor positions 32, structure and/or processing differences are introduced between the regions 30 and 32.
FIG. 3 illustrates one conventional method of causing lower threshold voltage transistors to be formed at certain locations 30 (logical zeros) while forming relative high threshold voltage transistors at other locations 32 (logical ones). In FIG. 3, buried bit lines 22, 24, 26 and 28 form the sources and drains of the memory FETs, oxide layer 40 forms the gate insulator for the FETs, and word line WL1 is the gate for the FETs. For those positions 30 at which a lower threshold voltage transistor is to be formed, the insulation layer 42 formed between the adjacent bit line implantations is made thin. For example, insulation layer 42 is silicon oxide formed to a conventional gate oxide thickness. For those positions 32 at which a relatively high threshold voltage transistor is to be formed, the insulation layer 44 between adjacent bit line implantations is made sufficiently thick that the FET consisting of bit lines 24 and 26 (source and drain regions), insulator 44 and gate WL1 has a measurably higher threshold voltage. Accordingly, programming for the FIG. 3 ROM type of FET is accomplished by forming thick insulating films over the channel regions where high threshold voltage FETs are to be formed and by growing thin insulating films over those FET channel regions where lower threshold voltage FETs are to be formed. Programming the FIG. 3 mask ROM typically requires the formation of a mask which exposes those potential channel regions at which thick oxides are to be formed, growth of a thick oxide, removal of the mask, and growth of thinner gate oxides over the locations at which low threshold voltage FETs are to be formed. This programming technique relies on the precise alignment of the mask with respect to the implantations to ensure that the thin oxide layer completely covers the channel regions at the appropriate positions. Misalignment in any direction can alter the threshold voltage characteristics of either the high threshold voltage FETs or the low threshold voltage FETs, lowering or increasing the threshold voltages of the FETs in a manner that makes data read out more difficult or more prone to errors. In addition, it is difficult to form sufficiently thick insulating films for small cell sizes, so that it is difficult to increase the cell density using this programming technique. As such, it is increasingly difficult to implement this programming technique for smaller design rules.
FIG. 4 illustrates a second method for selecting the threshold voltage characteristics of FETs to program the ROM illustrated in FIGS. 1 and 2. The FIG. 4 ROM has a uniformly thin insulation layer over all of the channel regions of the FETs in the matrix. The threshold voltages of the FETs are selected by implanting different impurity levels into the channel regions of the transistors. For example, if the transistor would normally require a threshold adjust implant for acceptable operation, then programming of the ROM might consist of implanting an appropriate level of dopants into the channel regions of the FETs that have low threshold voltages (logical zeros) and no implant is made into the channel regions of the FETs that are to have high threshold voltages (logical ones). If, on the other hand, no implant is necessary to enable the normal operation of a FET or if the difference between an unimplanted FET and a FET with a threshold adjust implant is too small to allow discrimination between implanted and unimplanted FETs, then an implant is made into the channels of those FETs that are to have high threshold voltages.
The processes for forming and programming the FIG. 4 ROM are now described. First, a mask is formed using photolithography on the substrate to expose the portions of the substrate into which dopants are implanted to define the buried N.sup.+ bit line regions. After the mask is removed, a uniform gate oxide is grown on the surface of the substrate, and then a layer of polysilicon is deposited over the gate oxide layer and the entire gate polysilicon layer is doped N-type with, for example, a phosphorus implant or by diffusion from POCl.sub.3. Typically, a layer of a refractory metal or a refractory metal silicide such as tungsten silicide is then deposited over the doped polysilicon layer to further reduce the resistivity of the gate material. A gate mask is formed and the tungsten silicide and doped polysilicon layer are etched to define the word lines which also serve as the gates for the FETs of the ROM. After the word lines are formed, additional processing is performed to form support circuitry and then a mask is formed to define the regions into which the ROM programming implantations are to be made. Alternately, the ROM programming implantation could be made at different points in the processing of the ROM.
When any type of selective channel implantation is used to program the FIG. 4 ROM, it is necessary to form a mask over the ROM which exposes the channels of the FETs into which the implantations are made. Several problems can occur in the conventional implantation programming technique which limit the extent to which this technology can be scaled down for use in smaller design rule devices. Implantation into the channel regions must be annealed to activate the impurities, and the implanted impurities tend to diffuse during the anneal. Diffusion from the implant regions parallel to the bit lines limits how closely word lines can be spaced, which in turn limits the extent to which the ROM cell can be miniaturized.
Other difficulties with the implantation programming technique arise from possible misalignment of the programming mask. Mask misalignment along the bit line direction, such as that illustrated in FIG. 5, can lead to the introduction of impurities from an intended implantation region into an adjacent region. If the adjacent region represents a memory location for which implantation should not be made, then this misalignment can generate an error, particularly when the misalignment is coupled with the subsequent diffusion of impurities. The need to provide an allowance for the type of misalignment illustrated in FIG. 5 and to provide an allowance for dopant diffusion limits how closely word lines can be spaced in the mask ROM.
A second type of mask error, arising either from misalignment or from a mask formation error, is illustrated in FIG. 6. Implantations into the channel region are not self-aligned to the buried N.sup.+ bit lines so that misalignment of the edge of the mask opening defining the implantation along the word line direction is a possible source of error. To limit the possibility of this error occurring, allowances must be made in the size of the implantation mask to increase the tolerance limits for mask placement. The provision of excess mask tolerances limits both how closely bit lines can be spaced and the width of the buried bit lines. Accordingly, it is desirable to develop a mask ROM less dependent on mask alignment and more compatible with increasing the storage density of a mask ROM.